s_brev_b32 GPU Native ISA AMD Scalar

Scalar Arithmetic

s_brev_b32

Reverse the order of bits in a scalar input and store the result into a scalar register.

Encoding

Binary Layout (AMD CDNA 5)
101111101
31:23
SDST
22:16
00000100
15:8
SSRC0
7:0
 

The ENC_SOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 4 in OP rebuilds 0xBE800400, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 8), AMD CDNA 3 (opcode 8), AMD CDNA 2 (opcode 8), AMD CDNA 1 (opcode 8), AMD RDNA 2 (opcode 11), AMD RDNA 1 (opcode 11). The same in AMD RDNA 4, AMD RDNA 3.5, AMD RDNA 3.

Format SOP1
Width 32 bits
Opcode 4
Identifier 0xBE800400

Operands

  • SDST
    Written. All scalar destination operands. Data format: Unsigned 32-bit integral data. (OPR_SDST, FMT_NUM_U32)
  • SSRC0
    Read. All scalar operands. Covers all operands that are allowed as scalar sources. Data format: Unsigned 32-bit integral data. (OPR_SSRC, FMT_NUM_U32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOP1 encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related PTX Concepts

Bit Reverse ↗
equivalent with restrictions
brev (PTX)

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

D0.u32[31 : 0] = S0.u32[0 : 31]

Example

s_brev_b32 s0, 0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources