s_bitreplicate_b64_b32 GPU Native ISA AMD Scalar

Scalar Arithmetic

s_bitreplicate_b64_b32

Substitute each bit of a 32 bit scalar input with two instances of itself and store the result into a 64 bit scalar register.

Encoding

Binary Layout (AMD CDNA 5)
101111101
31:23
SDST
22:16
00010100
15:8
SSRC0
7:0
 

The ENC_SOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 20 in OP rebuilds 0xBE801400, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 55), AMD CDNA 3 (opcode 55), AMD CDNA 2 (opcode 55), AMD CDNA 1 (opcode 55), AMD RDNA 2 (opcode 59), AMD RDNA 1 (opcode 59). The same in AMD RDNA 4, AMD RDNA 3.5, AMD RDNA 3.

Format SOP1
Width 32 bits
Opcode 20
Identifier 0xBE801400

Operands

  • SDST
    Written. All scalar destination operands. Data format: Unsigned 64-bit integral data. (OPR_SDST, FMT_NUM_U64)
  • SSRC0
    Read. All scalar operands. Covers all operands that are allowed as scalar sources. Data format: Unsigned 32-bit integral data. (OPR_SSRC, FMT_NUM_U32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOP1 encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

This opcode can be used to convert a quad mask into a pixel mask; given quad mask in s0, the following sequence produces a pixel mask in s2: s_bitreplicate_b64 s2, s0 s_bitreplicate_b64 s2, s2 To perform the inverse operation see S_QUADMASK_B64.

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

tmp = S0.u32; for i in 0 : 31 do D0.u64[i * 2] = tmp[i]; D0.u64[i * 2 + 1] = tmp[i] endfor

Example

s_bitreplicate_b64_b32 vcc, s2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources