s_bitreplicate_b64_b32 GPU Native ISA AMD Scalar

S BITREPLICATE B64 B32 Scalar Arithmetic

s_bitreplicate_b64_b32

Substitute each bit of a 32 bit scalar input with two instances of itself and store the result into a 64 bit scalar register.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (SOP1) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format SOP1
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

This opcode can be used to convert a quad mask into a pixel mask; given quad mask in s0, the following sequence produces a pixel mask in s2: s_bitreplicate_b64 s2, s0 s_bitreplicate_b64 s2, s2 To perform the inverse operation see S_QUADMASK_B64.

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

tmp = S0.u32; for i in 0 : 31 do D0.u64[i * 2] = tmp[i]; D0.u64[i * 2 + 1] = tmp[i] endfor

Example

s_bitreplicate_b64_b32 vcc, s2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.

Sources