s_andn2_wrexec_b64 GPU Native ISA AMD Scalar

Scalar Arithmetic

s_andn2_wrexec_b64

Calculate bitwise AND on the scalar input and the negation of the EXEC mask, store the calculated result into the EXEC mask and also into the scalar…

Also written as s_and_not1_wrexec_b64. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD CDNA 4)
101111101
31:23
SDST
22:16
00110110
15:8
SSRC0
7:0
 

The ENC_SOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 54 in OP rebuilds 0xBE803600, an identifier AMD lists for this encoding. Not the same in every generation: AMD RDNA 2 (opcode 58), AMD RDNA 1 (opcode 58). The same in AMD CDNA 3, AMD CDNA 2, AMD CDNA 1.

Format SOP1
Width 32 bits
Opcode 54
Identifier 0xBE803600

Operands

  • SDST
    Written. N/A Data format: N/A (OPR_SREG, FMT_NUM_U64)
  • SSRC0
    Read. N/A Data format: N/A (OPR_SSRC, FMT_NUM_U64)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOP1 encoding (AMD CDNA 4).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

In particular, the following sequence of waterfall code is optimized by using a WREXEC instead of two separate scalar ops: // V0 holds the index value per lane // save exec mask for restore at the end s_mov_b64 s2, exec // exec mask of remaining (unprocessed) threads s_mov_b64 s4, exec loop: // get the index value for the first active lane v_readfirstlane_b32 s0, v0 // find all other lanes with same index value v_cmpx_eq s0, v0 <OP> // do the operation using the current EXEC mask. S0 holds the index. // mask out thread that was just executed // s_andn2_b64 s4, s4, exec // s_mov_b64 exec, s4 s_andn2_wrexec_b64 s4, s4 // replaces above 2 ops // repeat until EXEC==0 s_cbranch_scc1 loop s_mov_b64 exec, s2

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Description

Calculate bitwise AND on the scalar input and the negation of the EXEC mask, store the calculated result into the EXEC mask and also into the scalar destination register, and set SCC iff the calculated result is nonzero. Unlike the SAVEEXEC series of opcodes, the value written to destination SGPRs is the result of the bitwise-op result. EXEC and the destination SGPRs have the same value at the end of this instruction. This instruction is intended to help accelerate waterfalling.

Semantics

EXEC.u64 = (S0.u64 & ~EXEC.u64); D0.u64 = EXEC.u64; SCC = EXEC.u64 != 0ULL

Example

s_andn2_wrexec_b64 s[0:1], 0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources