s_andn1_saveexec_b64 GPU Native ISA AMD Scalar

Scalar Arithmetic

s_andn1_saveexec_b64

Calculate bitwise AND on the EXEC mask and the negation of the scalar input, store the calculated result into the EXEC mask, set SCC iff the…

Also written as s_and_not0_saveexec_b64. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD CDNA 4)
101111101
31:23
SDST
22:16
00110011
15:8
SSRC0
7:0
 

The ENC_SOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 51 in OP rebuilds 0xBE803300, an identifier AMD lists for this encoding. Not the same in every generation: AMD RDNA 2 (opcode 55), AMD RDNA 1 (opcode 55). The same in AMD CDNA 3, AMD CDNA 2, AMD CDNA 1.

Format SOP1
Width 32 bits
Opcode 51
Identifier 0xBE803300

Operands

  • SDST
    Written. N/A Data format: N/A (OPR_SREG, FMT_NUM_U64)
  • SSRC0
    Read. N/A Data format: N/A (OPR_SSRC, FMT_NUM_U64)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOP1 encoding (AMD CDNA 4).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Description

Calculate bitwise AND on the EXEC mask and the negation of the scalar input, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register. The original EXEC mask is saved to the destination SGPRs before the bitwise operation is performed.

Semantics

saveexec = EXEC.u64; EXEC.u64 = (~S0.u64 & EXEC.u64); D0.u64 = saveexec.u64; SCC = EXEC.u64 != 0ULL

Example

s_andn1_saveexec_b64 s[0:1], 0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources