s_add_u64 GPU Native ISA AMD Scalar

Scalar Arithmetic

s_add_u64

AMDGPU SOP2 scalar instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)

Also written as s_add_nc_u64. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

AMD's machine-readable ISA specification lists this instruction as s_add_nc_u64, which has its own page here. The operands and layout below are from that entry.

Binary Layout (AMD CDNA 5)
10
31:30
1010011
29:23
SDST
22:16
SSRC1
15:8
SSRC0
7:0
 

The ENC_SOP2 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 83 in OP rebuilds 0xA9800000, an identifier AMD lists for this encoding. The same in AMD RDNA 4.

Format SOP2
Width 32 bits
Opcode 83
Identifier 0xA9800000

Operands

  • SDST
    Written. All scalar destination operands. Data format: Unsigned 64-bit integral data. (OPR_SDST, FMT_NUM_U64)
  • SSRC0
    Read. All scalar operands. Covers all operands that are allowed as scalar sources. Data format: Unsigned 64-bit integral data. (OPR_SSRC, FMT_NUM_U64)
  • SSRC1
    Read. All scalar operands. Covers all operands that are allowed as scalar sources. Data format: Unsigned 64-bit integral data. (OPR_SSRC, FMT_NUM_U64)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOP2 encoding (AMD CDNA 5).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Sources