s_abs_i32 GPU Native ISA AMD Scalar

Scalar Arithmetic

s_abs_i32

Compute the absolute value of a scalar input, store the result into a scalar register and set SCC iff the result is nonzero.

Encoding

Binary Layout (AMD CDNA 5)
101111101
31:23
SDST
22:16
00010101
15:8
SSRC0
7:0
 

The ENC_SOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 21 in OP rebuilds 0xBE801500, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 48), AMD CDNA 3 (opcode 48), AMD CDNA 2 (opcode 48), AMD CDNA 1 (opcode 48), AMD RDNA 2 (opcode 52), AMD RDNA 1 (opcode 52). The same in AMD RDNA 4, AMD RDNA 3.5, AMD RDNA 3.

Format SOP1
Width 32 bits
Opcode 21
Identifier 0xBE801500

Operands

  • SDST
    Written. All scalar destination operands. Data format: Signed 32-bit integral data. (OPR_SDST, FMT_NUM_I32)
  • SSRC0
    Read. All scalar operands. Covers all operands that are allowed as scalar sources. Data format: Signed 32-bit integral data. (OPR_SSRC, FMT_NUM_I32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOP1 encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

D0.i32 = S0.i32 < 0 ? -S0.i32 : S0.i32; SCC = D0.i32 != 0

Example

S_ABS_I32(0x00000001) => 0x00000001
S_ABS_I32(0x7fffffff) => 0x7fffffff
S_ABS_I32(0x80000000) => 0x80000000     // Note this is negative!
S_ABS_I32(0x80000001) => 0x7fffffff

Reproduced from AMD's official "AMD Instinct MI300" ISA Reference Guide for technical accuracy.

Sources