s_andn1_wrexec_b32 GPU Native ISA AMD Scalar

Scalar Arithmetic

s_andn1_wrexec_b32

Calculate bitwise AND on the EXEC mask and the negation of the scalar input, store the calculated result into the EXEC mask and also into the scalar…

Also written as s_and_not0_wrexec_b32. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD RDNA 2)
101111101
31:23
SDST
22:16
01000110
15:8
SSRC0
7:0
 

The ENC_SOP1 layout from AMD's machine-readable ISA specification (AMD RDNA 2). Opcode 70 in OP rebuilds 0xBE804600, an identifier AMD lists for this encoding. The same in AMD RDNA 1.

Format SOP1
Width 32 bits
Opcode 70
Identifier 0xBE804600

Operands

  • SDST
    Written. N/A Data format: N/A (OPR_SREG, FMT_NUM_U32)
  • SSRC0
    Read. Simple scalar operands, plus SRC_LITERAL. Covers all operands that are allowed as scalar sources except for SRC_LDS_DIRECT. Data format: N/A (OPR_SSRC_NOLDS, FMT_NUM_U32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOP1 encoding (AMD RDNA 2).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Description

Calculate bitwise AND on the EXEC mask and the negation of the scalar input, store the calculated result into the EXEC mask and also into the scalar destination register, and set SCC iff the calculated result is nonzero.

Example

s_andn1_wrexec_b32 s0, 0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources