s_barrier_join GPU Native ISA AMD Scalar

Scalar Arithmetic

s_barrier_join

AMDGPU SOP1 scalar instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)

Encoding

Binary Layout (AMD CDNA 5)
101111101
31:23
SDST
22:16
01010010
15:8
SSRC0
7:0
 

The ENC_SOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 82 in OP rebuilds 0xBE805200, an identifier AMD lists for this encoding. No other generation in the specification defines this instruction.

Format SOP1
Width 32 bits
Opcode 82
Identifier 0xBE805200

Operands

  • SSRC0
    Read. N/A Data format: 32 bits of arbitrary data. (OPR_SSRC_BARRIER_ID, FMT_NUM_B32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOP1 encoding (AMD CDNA 5).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Example

s_barrier_join 0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx13_asm_sop1.s). Not from an AMD document, and not authored here.

Sources