s_cbranch_g_fork GPU Native ISA AMD Scalar

Scalar Arithmetic

s_cbranch_g_fork

Conditional branch using branch-stack.

Encoding

Binary Layout (AMD CDNA 4)
10
31:30
0101001
29:23
SDST
22:16
SSRC1
15:8
SSRC0
7:0
 

The ENC_SOP2 layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 41 in OP rebuilds 0x94800000, an identifier AMD lists for this encoding. The same in the other 3 generations that define it.

Format SOP2
Width 32 bits
Opcode 41
Identifier 0x94800000

Operands

  • SSRC0
    Read. N/A Data format: N/A (OPR_SSRC_NOLIT, FMT_NUM_B64)
  • SSRC1
    Read. N/A Data format: N/A (OPR_SSRC_NOLIT, FMT_NUM_B64)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOP2 encoding (AMD CDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Example

s_cbranch_g_fork 0, s[4:5]

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx7_asm_sop2.s). Not from an AMD document, and not authored here.

Sources