s_cmov_b32 GPU Native ISA AMD Scalar

Scalar Arithmetic

s_cmov_b32

Move scalar input into a scalar register iff SCC is nonzero.

Encoding

Binary Layout (AMD CDNA 5)
101111101
31:23
SDST
22:16
00000010
15:8
SSRC0
7:0
 

The ENC_SOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 2 in OP rebuilds 0xBE800200, an identifier AMD lists for this encoding. Not the same in every generation: AMD RDNA 2 (opcode 5), AMD RDNA 1 (opcode 5). The same in AMD CDNA 4, AMD CDNA 3, AMD CDNA 2, AMD CDNA 1, AMD RDNA 4, AMD RDNA 3.5, AMD RDNA 3.

Format SOP1
Width 32 bits
Opcode 2
Identifier 0xBE800200

Operands

  • SDST
    Written. All scalar destination operands. Data format: 32 bits of arbitrary data. (OPR_SDST, FMT_NUM_B32)
  • SSRC0
    Read. All scalar operands. Covers all operands that are allowed as scalar sources. Data format: 32 bits of arbitrary data. (OPR_SSRC, FMT_NUM_B32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOP1 encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

if SCC then D0.b32 = S0.b32 endif

Example

s_cmov_b32 s0, 0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources