s_cmovk_i32 GPU Native ISA AMD Scalar

Scalar Arithmetic

s_cmovk_i32

Move the sign extension of a literal 16-bit constant into a scalar register iff SCC is nonzero.

Encoding

Binary Layout (AMD CDNA 5)
1011
31:28
00010
27:23
SDST
22:16
SIMM16
15:0
 

The ENC_SOPK layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 2 in OP rebuilds 0xB1000000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 1), AMD CDNA 3 (opcode 1), AMD CDNA 2 (opcode 1), AMD CDNA 1 (opcode 1). The same in AMD RDNA 4, AMD RDNA 3.5, AMD RDNA 3, AMD RDNA 2, AMD RDNA 1.

Format SOPK
Width 32 bits
Opcode 2
Identifier 0xB1000000

Operands

  • SDST
    Written. All scalar destination operands. Data format: Signed 32-bit integral data. (OPR_SDST, FMT_NUM_I32)
  • SIMM16
    Read. 16-bit integer constant. Data format: Signed 16-bit integral data. (OPR_SIMM16, FMT_NUM_I16)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOPK encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

if SCC then D0.i32 = 32'I(signext(S0.i16)) endif

Example

s_cmovk_i32 s0, 0x1234

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources