s_cmovk_i32 GPU Native ISA AMD Scalar
S CMOVK I32 Scalar Arithmetic
s_cmovk_i32
Move the sign extension of a literal 16-bit constant into a scalar register iff SCC is nonzero.
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (SOPK)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
Related
More in Scalar Arithmetic
Reference
AMDGPU / GFX ISA
Semantics
if SCC then
D0.i32 = 32'I(signext(S0.i16))
endif
Example
s_cmovk_i32 s0, 0x1234A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 109. - LLVM MC assembler tests for AMDGPU (gfx11) ↗ - LLVM Project