s_clz_i32_u64 GPU Native ISA AMD Scalar

Scalar Arithmetic

s_clz_i32_u64

Count the number of leading "0" bits before the first "1" in a scalar input and store the result into a scalar register.

Also written as s_flbit_i32_b64. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD CDNA 5)
101111101
31:23
SDST
22:16
00001011
15:8
SSRC0
7:0
 

The ENC_SOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 11 in OP rebuilds 0xBE800B00, an identifier AMD lists for this encoding. The same in the other 3 generations that define it.

Format SOP1
Width 32 bits
Opcode 11
Identifier 0xBE800B00

Operands

  • SDST
    Written. All scalar destination operands. Data format: Signed 32-bit integral data. (OPR_SDST, FMT_NUM_I32)
  • SSRC0
    Read. All scalar operands. Covers all operands that are allowed as scalar sources. Data format: Unsigned 64-bit integral data. (OPR_SSRC, FMT_NUM_U64)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOP1 encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Description

Count the number of leading "0" bits before the first "1" in a scalar input and store the result into a scalar register. Store -1 if there are no "1" bits.

Example

s_clz_i32_u64 s105, vcc

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources