s_flbit_i32_b64 GPU Native ISA AMD Scalar
S FLBIT I32 B64 Scalar Arithmetic
s_flbit_i32_b64
Count the number of leading "0" bits before the first "1" in a scalar input and store the result into a scalar register.
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (SOP1)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
Related
More in Scalar Arithmetic
Reference
AMDGPU / GFX ISA
Description
Count the number of leading "0" bits before the first "1" in a scalar input and store the result into a scalar register. Store -1 if there are no "1" bits.
Semantics
tmp = -1;
// Set if no ones are found
for i in 0 : 63 do
// Search from MSB
if S0.u64[63 - i] == 1'1U then
tmp = i;
break
endif
endfor;
D0.i32 = tmp
Example
s_flbit_i32_b64 s0, 0A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 121. - LLVM MC assembler tests for AMDGPU (gfx11) ↗ - LLVM Project