s_flbit_i32_i64 GPU Native ISA AMD Scalar

Scalar Arithmetic

s_flbit_i32_i64

Count the number of leading bits that are the same as the sign bit of a scalar input and store the result into a scalar register.

Also written as s_cls_i32_i64. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD CDNA 4)
101111101
31:23
SDST
22:16
00010101
15:8
SSRC0
7:0
 

The ENC_SOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 21 in OP rebuilds 0xBE801500, an identifier AMD lists for this encoding. Not the same in every generation: AMD RDNA 2 (opcode 24), AMD RDNA 1 (opcode 24). The same in AMD CDNA 3, AMD CDNA 2, AMD CDNA 1.

Format SOP1
Width 32 bits
Opcode 21
Identifier 0xBE801500

Operands

  • SDST
    Written. N/A Data format: N/A (OPR_SDST, FMT_NUM_I32)
  • SSRC0
    Read. N/A Data format: N/A (OPR_SSRC, FMT_NUM_I64)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOP1 encoding (AMD CDNA 4).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Description

Count the number of leading bits that are the same as the sign bit of a scalar input and store the result into a scalar register. Store -1 if all input bits are the same.

Semantics

tmp = -1; // Set if all bits are the same for i in 1 : 63 do // Search from MSB if S0.u64[63 - i] != S0.u64[63] then tmp = i; break endif endfor; D0.i32 = tmp

Example

s_flbit_i32_i64 s0, 0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources