s_max_i32 GPU Native ISA AMD Scalar
S MAX I32 Scalar Arithmetic
s_max_i32
Select the maximum of two signed 32-bit integer inputs, store the selected value into a scalar register and set SCC iff the first value is selected.
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (SOP2)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
Related
More in Scalar Arithmetic
Reference
AMDGPU / GFX ISA
Semantics
SCC = S0.i32 >= S1.i32;
D0.i32 = SCC ? S0.i32 : S1.i32
Example
s_max_i32 s0, 0, s2A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 98. - LLVM MC assembler tests for AMDGPU (gfx11) ↗ - LLVM Project