s_movk_i32 GPU Native ISA AMD Scalar

Scalar Arithmetic

s_movk_i32

Sign extend a literal 16-bit constant and store the result into a scalar register.

Encoding

Binary Layout (AMD CDNA 5)
1011
31:28
00000
27:23
SDST
22:16
SIMM16
15:0
 

The ENC_SOPK layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 0 in OP rebuilds 0xB0000000, an identifier AMD lists for this encoding. The same in the other 9 generations that define it.

Format SOPK
Width 32 bits
Opcode 0
Identifier 0xB0000000

Operands

  • SDST
    Written. All scalar destination operands. Data format: Signed 32-bit integral data. (OPR_SDST, FMT_NUM_I32)
  • SIMM16
    Read. 16-bit integer constant. Data format: Signed 16-bit integral data. (OPR_SIMM16, FMT_NUM_I16)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOPK encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

D0.i32 = 32'I(signext(S0.i16))

Example

s_movk_i32 s0, 0x1234

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources