s_mul_i32 GPU Native ISA AMD Scalar

S MUL I32 Scalar Arithmetic

s_mul_i32 SDST, S0, S1

Multiply two 32-bit signed scalar operands, wavefront-uniform, low 32 bits of the product.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (SOP2) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format SOP2
Width 32 bits
Execution Unit Scalar ALU
Register Classes SGPR

Operands

  • SDST
    Destination SGPR
  • S0
    First source SGPR/constant
  • S1
    Second source SGPR/constant

GFX Target Compatibility

TargetSupport
gfx942✅ Supported
gfx1100✅ Supported

Related PTX Concepts

Integer Multiplication ↗
equivalent with restrictions
mul (PTX)

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Description

Multiply two signed 32-bit integer inputs and store the result into a scalar register.

Semantics

SDST = lo32(S0.i32 * S1.i32).

Example

s_mul_i32  s2, s0, s1   // s2 = low32(s0 * s1)

Original illustrative example, written for this site (not reproduced from a specific AMD document).

Sources