s_mul_i32 GPU Native ISA AMD Scalar

Scalar Arithmetic

s_mul_i32 SDST, S0, S1

Multiply two 32-bit signed scalar operands, wavefront-uniform, low 32 bits of the product.

Encoding

Binary Layout (AMD CDNA 5)
10
31:30
0101100
29:23
SDST
22:16
SSRC1
15:8
SSRC0
7:0
 

The ENC_SOP2 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 44 in OP rebuilds 0x96000000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 36), AMD CDNA 3 (opcode 36), AMD CDNA 2 (opcode 36), AMD CDNA 1 (opcode 36), AMD RDNA 2 (opcode 38), AMD RDNA 1 (opcode 38). The same in AMD RDNA 4, AMD RDNA 3.5, AMD RDNA 3.

Format SOP2
Width 32 bits
Opcode 44
Identifier 0x96000000
Execution Unit Scalar ALU
Register Classes SGPR

Operands

  • SDST
    Destination SGPR
  • S0
    First source SGPR/constant
  • S1
    Second source SGPR/constant

GFX Target Compatibility

TargetSupport
gfx942✅ Supported
gfx1100✅ Supported

Related PTX Concepts

Integer Multiplication ↗
equivalent with restrictions
mul (PTX)

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Description

Multiply two signed 32-bit integer inputs and store the result into a scalar register.

Semantics

SDST = lo32(S0.i32 * S1.i32).

Example

s_mul_i32  s2, s0, s1   // s2 = low32(s0 * s1)

Original illustrative example, written for this site (not reproduced from a specific AMD document).

Sources