s_movrelsd_2_b32 GPU Native ISA AMD Scalar

Scalar Arithmetic

s_movrelsd_2_b32

Move data from a relatively-indexed scalar register into another relatively-indexed scalar register, using different offsets for each index.

Encoding

Binary Layout (AMD CDNA 5)
101111101
31:23
SDST
22:16
01000100
15:8
SSRC0
7:0
 

The ENC_SOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 68 in OP rebuilds 0xBE804400, an identifier AMD lists for this encoding. Not the same in every generation: AMD RDNA 2 (opcode 73), AMD RDNA 1 (opcode 73). The same in AMD RDNA 4, AMD RDNA 3.5, AMD RDNA 3.

Format SOP1
Width 32 bits
Opcode 68
Identifier 0xBE804400

Operands

  • SDST
    Written. Any scalar GPR operand including VCC and NULL. Data format: 32 bits of arbitrary data. (OPR_SREG, FMT_NUM_B32)
  • SSRC0
    Read. Any scalar GPR operand including VCC and NULL. Data format: 32 bits of arbitrary data. (OPR_SREG, FMT_NUM_B32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOP1 encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Example

s_movrelsd_2_b32 s0, s1

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources