s_movrels_b32 GPU Native ISA AMD Scalar

Scalar Arithmetic

s_movrels_b32

Move data from a relatively-indexed scalar register into another scalar register.

Encoding

Binary Layout (AMD CDNA 5)
101111101
31:23
SDST
22:16
01000000
15:8
SSRC0
7:0
 

The ENC_SOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 64 in OP rebuilds 0xBE804000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 42), AMD CDNA 3 (opcode 42), AMD CDNA 2 (opcode 42), AMD CDNA 1 (opcode 42), AMD RDNA 2 (opcode 46), AMD RDNA 1 (opcode 46). The same in AMD RDNA 4, AMD RDNA 3.5, AMD RDNA 3.

Format SOP1
Width 32 bits
Opcode 64
Identifier 0xBE804000

Operands

  • SDST
    Written. All scalar destination operands. Data format: 32 bits of arbitrary data. (OPR_SDST, FMT_NUM_B32)
  • SSRC0
    Read. Any scalar GPR operand including VCC and NULL. Data format: 32 bits of arbitrary data. (OPR_SREG, FMT_NUM_B32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOP1 encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Example: The following instruction sequence performs the move s5 <= s17: s_mov_b32 m0, 10 s_movrels_b32 s5, s7

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

addr = SRC0.u32; // Raw value from instruction addr += M0.u32[31 : 0]; D0.b32 = SGPR[addr].b32

Example

s_movrels_b32 s0, s1

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources