s_movrels_b32 GPU Native ISA AMD Scalar
S MOVRELS B32 Scalar Arithmetic
s_movrels_b32
Move data from a relatively-indexed scalar register into another scalar register.
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (SOP1)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
Example: The following instruction sequence performs the move s5 <= s17: s_mov_b32 m0, 10 s_movrels_b32 s5, s7
Related
More in Scalar Arithmetic
Reference
AMDGPU / GFX ISA
Semantics
addr = SRC0.u32;
// Raw value from instruction
addr += M0.u32[31 : 0];
D0.b32 = SGPR[addr].b32
Example
s_movrels_b32 s0, s1A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 127. - LLVM MC assembler tests for AMDGPU (gfx11) ↗ - LLVM Project