s_maximum_f32 GPU Native ISA AMD Scalar

Scalar Arithmetic

s_maximum_f32

Select the IEEE maximum() of two single-precision float inputs and store the selected value into a scalar register.

Encoding

Binary Layout (AMD CDNA 5)
10
31:30
1010000
29:23
SDST
22:16
SSRC1
15:8
SSRC0
7:0
 

The ENC_SOP2 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 80 in OP rebuilds 0xA8000000, an identifier AMD lists for this encoding. The same in AMD RDNA 4.

Format SOP2
Width 32 bits
Opcode 80
Identifier 0xA8000000

Operands

  • SDST
    Written. All scalar destination operands. Data format: 32-bit single-precision floating point value. (OPR_SDST, FMT_NUM_F32)
  • SSRC0
    Read. All scalar operands. Covers all operands that are allowed as scalar sources. Data format: 32-bit single-precision floating point value. (OPR_SSRC, FMT_NUM_F32)
  • SSRC1
    Read. All scalar operands. Covers all operands that are allowed as scalar sources. Data format: 32-bit single-precision floating point value. (OPR_SSRC, FMT_NUM_F32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOP2 encoding (AMD CDNA 5).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Example

s_maximum_f32 s5, 0, s2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx12_asm_sop2.s). Not from an AMD document, and not authored here.

Sources