s_mul_u64 GPU Native ISA AMD Scalar

Scalar Arithmetic

s_mul_u64

Multiply two unsigned 64-bit integer inputs and store the result into a scalar register.

Encoding

Binary Layout (AMD CDNA 5)
10
31:30
1010101
29:23
SDST
22:16
SSRC1
15:8
SSRC0
7:0
 

The ENC_SOP2 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 85 in OP rebuilds 0xAA800000, an identifier AMD lists for this encoding. The same in AMD RDNA 4.

Format SOP2
Width 32 bits
Opcode 85
Identifier 0xAA800000

Operands

  • SDST
    Written. All scalar destination operands. Data format: Unsigned 64-bit integral data. (OPR_SDST, FMT_NUM_U64)
  • SSRC0
    Read. All scalar operands. Covers all operands that are allowed as scalar sources. Data format: Unsigned 64-bit integral data. (OPR_SSRC, FMT_NUM_U64)
  • SSRC1
    Read. All scalar operands. Covers all operands that are allowed as scalar sources. Data format: Unsigned 64-bit integral data. (OPR_SSRC, FMT_NUM_U64)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOP2 encoding (AMD CDNA 5).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Example

s_mul_u64 s[0:1], 0, s[2:3]

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx12_asm_sop2.s). Not from an AMD document, and not authored here.

Sources