s_mul_hi_u32 GPU Native ISA AMD Scalar

Scalar Arithmetic

s_mul_hi_u32

Multiply two unsigned integers and store the high 32 bits of the result into a scalar register.

Encoding

Binary Layout (AMD CDNA 5)
10
31:30
0101101
29:23
SDST
22:16
SSRC1
15:8
SSRC0
7:0
 

The ENC_SOP2 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 45 in OP rebuilds 0x96800000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 44), AMD CDNA 3 (opcode 44), AMD CDNA 2 (opcode 44), AMD CDNA 1 (opcode 44), AMD RDNA 2 (opcode 53), AMD RDNA 1 (opcode 53). The same in AMD RDNA 4, AMD RDNA 3.5, AMD RDNA 3.

Format SOP2
Width 32 bits
Opcode 45
Identifier 0x96800000

Operands

  • SDST
    Written. All scalar destination operands. Data format: Unsigned 32-bit integral data. (OPR_SDST, FMT_NUM_U32)
  • SSRC0
    Read. All scalar operands. Covers all operands that are allowed as scalar sources. Data format: Unsigned 32-bit integral data. (OPR_SSRC, FMT_NUM_U32)
  • SSRC1
    Read. All scalar operands. Covers all operands that are allowed as scalar sources. Data format: Unsigned 32-bit integral data. (OPR_SSRC, FMT_NUM_U32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOP2 encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

D0.u32 = 32'U((64'U(S0.u32) * 64'U(S1.u32)) >> 32U)

Example

s_mul_hi_u32 s0, 0, s2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources