s_movreld_b64 GPU Native ISA AMD Scalar
S MOVRELD B64 Scalar Arithmetic
s_movreld_b64
Move data from a scalar input into a relatively-indexed scalar register.
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (SOP1)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
Related
More in Scalar Arithmetic
Reference
AMDGPU / GFX ISA
Description
Move data from a scalar input into a relatively-indexed scalar register. The index in M0.u and the operand address in DST.u must be even for this operation.
Semantics
addr = DST.u32;
// Raw value from instruction
addr += M0.u32[31 : 0];
SGPR[addr].b64 = S0.b64
Example
s_movreld_b64 s[0:1], 0A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 128. - LLVM MC assembler tests for AMDGPU (gfx11) ↗ - LLVM Project