s_nand_saveexec_b32 GPU Native ISA AMD Scalar

Scalar Arithmetic

s_nand_saveexec_b32

Calculate bitwise NAND on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is…

Encoding

Binary Layout (AMD CDNA 5)
101111101
31:23
SDST
22:16
00100110
15:8
SSRC0
7:0
 

The ENC_SOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 38 in OP rebuilds 0xBE802600, an identifier AMD lists for this encoding. Not the same in every generation: AMD RDNA 2 (opcode 65), AMD RDNA 1 (opcode 65). The same in AMD RDNA 4, AMD RDNA 3.5, AMD RDNA 3.

Format SOP1
Width 32 bits
Opcode 38
Identifier 0xBE802600

Operands

  • SDST
    Written. Any scalar GPR operand including VCC and NULL. Data format: Unsigned 32-bit integral data. (OPR_SREG, FMT_NUM_U32)
  • SSRC0
    Read. All scalar operands. Covers all operands that are allowed as scalar sources. Data format: Unsigned 32-bit integral data. (OPR_SSRC, FMT_NUM_U32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOP1 encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Description

Calculate bitwise NAND on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register.

Example

s_nand_saveexec_b32 s0, 0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources