s_pack_hl_b32_b16 GPU Native ISA AMD Scalar

S PACK HL B32 B16 Scalar Arithmetic

s_pack_hl_b32_b16

Pack two 16-bit scalar values into a scalar register.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (SOP2) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format SOP2
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Example

s_pack_hl_b32_b16 s5, s1, s2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.

Sources