s_sext_i32_i8 GPU Native ISA AMD Scalar

Scalar Arithmetic

s_sext_i32_i8

Sign extend a signed 8 bit scalar input to 32 bits and store the result into a scalar register.

Encoding

Binary Layout (AMD CDNA 5)
101111101
31:23
SDST
22:16
00001110
15:8
SSRC0
7:0
 

The ENC_SOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 14 in OP rebuilds 0xBE800E00, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 22), AMD CDNA 3 (opcode 22), AMD CDNA 2 (opcode 22), AMD CDNA 1 (opcode 22), AMD RDNA 2 (opcode 25), AMD RDNA 1 (opcode 25). The same in AMD RDNA 4, AMD RDNA 3.5, AMD RDNA 3.

Format SOP1
Width 32 bits
Opcode 14
Identifier 0xBE800E00

Operands

  • SDST
    Written. All scalar destination operands. Data format: Signed 32-bit integral data. (OPR_SDST, FMT_NUM_I32)
  • SSRC0
    Read. All scalar operands. Covers all operands that are allowed as scalar sources. Data format: Signed 8-bit integral data. (OPR_SSRC, FMT_NUM_I8)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOP1 encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related PTX Concepts

Sign/Zero Extend ↗
equivalent with restrictions
szext (PTX)

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

D0.i32 = 32'I(signext(S0.i8))

Example

s_sext_i32_i8 s0, 0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources