s_sext_i32_i8 GPU Native ISA AMD Scalar

S SEXT I32 I8 Scalar Arithmetic

s_sext_i32_i8

Sign extend a signed 8 bit scalar input to 32 bits and store the result into a scalar register.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (SOP1) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format SOP1
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related PTX Concepts

Sign/Zero Extend ↗
equivalent with restrictions
szext (PTX)

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

D0.i32 = 32'I(signext(S0.i8))

Example

s_sext_i32_i8 s0, 0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.

Sources