s_sub_i32 GPU Native ISA AMD Scalar

Scalar Arithmetic

s_sub_i32

Subtract the second signed 32-bit integer input from the first input, store the result into a scalar register and store the carry-out bit into SCC.

Also written as s_sub_co_i32. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD CDNA 4)
10
31:30
0000011
29:23
SDST
22:16
SSRC1
15:8
SSRC0
7:0
 

The ENC_SOP2 layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 3 in OP rebuilds 0x81800000, an identifier AMD lists for this encoding. The same in the other 7 generations that define it.

Format SOP2
Width 32 bits
Opcode 3
Identifier 0x81800000

Operands

  • SDST
    Written. N/A Data format: N/A (OPR_SDST, FMT_NUM_I32)
  • SSRC0
    Read. N/A Data format: N/A (OPR_SSRC, FMT_NUM_I32)
  • SSRC1
    Read. N/A Data format: N/A (OPR_SSRC, FMT_NUM_I32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOP2 encoding (AMD CDNA 4).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

This opcode is not suitable for use with S_SUBB_U32 for implementing 64-bit operations.

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

tmp = S0.i32 - S1.i32; SCC = ((S0.u32[31] != S1.u32[31]) && (S0.u32[31] != tmp.u32[31])); // signed overflow. D0.i32 = tmp.i32

Example

s_sub_i32 s0, 0, s2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources