s_sub_nc_u64 GPU Native ISA AMD Scalar

Scalar Arithmetic

s_sub_nc_u64

Subtract the second unsigned 64-bit integer input from the first input and store the result into a scalar register.

Also written as s_sub_u64. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD CDNA 5)
10
31:30
1010100
29:23
SDST
22:16
SSRC1
15:8
SSRC0
7:0
 

The ENC_SOP2 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 84 in OP rebuilds 0xAA000000, an identifier AMD lists for this encoding. The same in AMD RDNA 4.

Format SOP2
Width 32 bits
Opcode 84
Identifier 0xAA000000

Operands

  • SDST
    Written. All scalar destination operands. Data format: Unsigned 64-bit integral data. (OPR_SDST, FMT_NUM_U64)
  • SSRC0
    Read. All scalar operands. Covers all operands that are allowed as scalar sources. Data format: Unsigned 64-bit integral data. (OPR_SSRC, FMT_NUM_U64)
  • SSRC1
    Read. All scalar operands. Covers all operands that are allowed as scalar sources. Data format: Unsigned 64-bit integral data. (OPR_SSRC, FMT_NUM_U64)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOP2 encoding (AMD CDNA 5).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Example

s_sub_nc_u64 s[0:1], 0, s[2:3]

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx12_asm_sop2.s). Not from an AMD document, and not authored here.

Sources