s_subvector_loop_end GPU Native ISA AMD Scalar

Scalar Arithmetic

s_subvector_loop_end

End execution of a subvector block of code.

Encoding

Binary Layout (AMD RDNA 2)
1011
31:28
11100
27:23
SDST
22:16
SIMM16
15:0
 

The ENC_SOPK layout from AMD's machine-readable ISA specification (AMD RDNA 2). Opcode 28 in OP rebuilds 0xBE000000, an identifier AMD lists for this encoding. The same in AMD RDNA 1.

Format SOPK
Width 32 bits
Opcode 28
Identifier 0xBE000000

Operands

  • SDST
    Written. N/A Data format: N/A (OPR_SDST, FMT_NUM_B32)
  • SIMM16
    Read. A relative jump offset. Data format: N/A (OPR_LABEL, FMT_NUM_I16)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOPK encoding (AMD RDNA 2).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Example

s_subvector_loop_end s0, 0x1234

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources