s_swappc_b64 GPU Native ISA AMD Scalar

S SWAPPC B64 Scalar Arithmetic

s_swappc_b64

Store the address of the next instruction to a scalar register and then jump to an address specified in the scalar input.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (SOP1) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format SOP1
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

This instruction must be 4 bytes.

Related PTX Concepts

Function Call ↗
equivalent with restrictions
call (PTX)

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Description

Store the address of the next instruction to a scalar register and then jump to an address specified in the scalar input. The argument is a byte address of the instruction to jump to. The byte address of the instruction immediately following this instruction is saved to the destination.

Semantics

jump_addr = S0.i64; D0.i64 = PC + 4LL; PC = jump_addr.i64

Example

s_swappc_b64 s[0:1], vcc

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.

Sources