s_sendmsg_rtn_b64 GPU Native ISA AMD Scalar

Scalar Arithmetic

s_sendmsg_rtn_b64

Send a message to upstream control hardware.

Encoding

Binary Layout (AMD CDNA 5)
101111101
31:23
SDST
22:16
01001101
15:8
SSRC0
7:0
 

The ENC_SOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 77 in OP rebuilds 0xBE804D00, an identifier AMD lists for this encoding. The same in the other 3 generations that define it.

Format SOP1
Width 32 bits
Opcode 77
Identifier 0xBE804D00

Operands

  • SDST
    Written. All scalar destination operands. Data format: 64 bits of arbitrary data. (OPR_SDST, FMT_NUM_B64)
  • SSRC0
    Read. Send a message back to upstream control hardware, with a return value expected. Data format: 32 bits of arbitrary data. (OPR_SENDMSG_RTN, FMT_NUM_B32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOP1 encoding (AMD CDNA 5).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Example

s_sendmsg_rtn_b64 vcc, 0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx13_asm_sop1.s). Not from an AMD document, and not authored here.

Sources