s_quadmask_b64 GPU Native ISA AMD Scalar

Scalar Arithmetic

s_quadmask_b64

Reduce a pixel mask from the scalar input into a quad mask, store the result in a scalar register and set SCC iff the result is nonzero.

Encoding

Binary Layout (AMD CDNA 5)
101111101
31:23
SDST
22:16
00011011
15:8
SSRC0
7:0
 

The ENC_SOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 27 in OP rebuilds 0xBE801B00, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 41), AMD CDNA 3 (opcode 41), AMD CDNA 2 (opcode 41), AMD CDNA 1 (opcode 41), AMD RDNA 2 (opcode 45), AMD RDNA 1 (opcode 45). The same in AMD RDNA 4, AMD RDNA 3.5, AMD RDNA 3.

Format SOP1
Width 32 bits
Opcode 27
Identifier 0xBE801B00

Operands

  • SDST
    Written. All scalar destination operands. Data format: Unsigned 64-bit integral data. (OPR_SDST, FMT_NUM_U64)
  • SSRC0
    Read. All scalar operands. Covers all operands that are allowed as scalar sources. Data format: Unsigned 64-bit integral data. (OPR_SSRC, FMT_NUM_U64)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOP1 encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

To perform the inverse operation see S_BITREPLICATE_B64_B32.

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

tmp = 0ULL; for i in 0 : 15 do tmp[i] = S0.u64[i * 4 +: 4] != 0ULL endfor; D0.u64 = tmp; SCC = D0.u64 != 0ULL

Example

s_quadmask_b64 s[0:1], 0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources