s_quadmask_b64 GPU Native ISA AMD Scalar
S QUADMASK B64 Scalar Arithmetic
s_quadmask_b64
Reduce a pixel mask from the scalar input into a quad mask, store the result in a scalar register and set SCC iff the result is nonzero.
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (SOP1)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
To perform the inverse operation see S_BITREPLICATE_B64_B32.
Related
More in Scalar Arithmetic
Reference
AMDGPU / GFX ISA
Semantics
tmp = 0ULL;
for i in 0 : 15 do
tmp[i] = S0.u64[i * 4 +: 4] != 0ULL
endfor;
D0.u64 = tmp;
SCC = D0.u64 != 0ULL
Example
s_quadmask_b64 s[0:1], 0A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 127. - LLVM MC assembler tests for AMDGPU (gfx11) ↗ - LLVM Project