s_sub_f32 GPU Native ISA AMD Scalar

Scalar Arithmetic

s_sub_f32

Subtract the second floating point input from the first input and store the result in a scalar register.

Encoding

Binary Layout (AMD CDNA 5)
10
31:30
1000001
29:23
SDST
22:16
SSRC1
15:8
SSRC0
7:0
 

The ENC_SOP2 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 65 in OP rebuilds 0xA0800000, an identifier AMD lists for this encoding. The same in the other 2 generations that define it.

Format SOP2
Width 32 bits
Opcode 65
Identifier 0xA0800000

Operands

  • SDST
    Written. All scalar destination operands. Data format: 32-bit single-precision floating point value. (OPR_SDST, FMT_NUM_F32)
  • SSRC0
    Read. All scalar operands. Covers all operands that are allowed as scalar sources. Data format: 32-bit single-precision floating point value. (OPR_SSRC, FMT_NUM_F32)
  • SSRC1
    Read. All scalar operands. Covers all operands that are allowed as scalar sources. Data format: 32-bit single-precision floating point value. (OPR_SSRC, FMT_NUM_F32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOP2 encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Example

s_sub_f32 s5, 0, s2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx1150_asm_salu_float.s). Not from an AMD document, and not authored here.

Sources