s_sub_u32 GPU Native ISA AMD Scalar

S SUB U32 Scalar Arithmetic

s_sub_u32 SDST, S0, S1

Subtract two 32-bit unsigned scalar operands, wavefront-uniform.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (SOP2) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format SOP2
Width 32 bits
Execution Unit Scalar ALU
Register Classes SGPR

Operands

  • SDST
    Destination SGPR
  • S0
    Minuend SGPR/constant
  • S1
    Subtrahend SGPR/constant

GFX Target Compatibility

TargetSupport
gfx942✅ Supported
gfx1100✅ Supported

Related PTX Concepts

Integer Subtraction ↗
equivalent with restrictions
sub (PTX)
Subtract with Borrow-Out ↗
equivalent with restrictions
sub.cc (PTX)

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Description

Subtract the second unsigned 32-bit integer input from the first input, store the result into a scalar register and store the carry-out bit into SCC.

Semantics

SDST = S0.u32 - S1.u32; SCC = borrow-out.

Example

s_sub_u32  s2, s0, s1   // s2 = s0 - s1

Original illustrative example, written for this site (not reproduced from a specific AMD document).

Sources