s_xor_b32 GPU Native ISA AMD Scalar

S XOR B32 Scalar Arithmetic

s_xor_b32

Calculate bitwise XOR on two scalar inputs, store the result into a scalar register and set SCC iff the result is nonzero.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (SOP2) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format SOP2
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related PTX Concepts

Bitwise XOR ↗
equivalent with restrictions
xor (PTX)

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

D0.u32 = (S0.u32 ^ S1.u32); SCC = D0.u32 != 0U

Example

s_xor_b32 s0, 0, s2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.

Sources