s_setreg_b32 GPU Native ISA AMD Scalar

Scalar Arithmetic

s_setreg_b32

Write some or all of the LSBs of source argument into a hardware register.

Encoding

Binary Layout (AMD CDNA 5)
1011
31:28
10010
27:23
SDST
22:16
SIMM16
15:0
 

The ENC_SOPK layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 18 in OP rebuilds 0xB9000000, an identifier AMD lists for this encoding. Not the same in every generation: AMD RDNA 2 (opcode 19), AMD RDNA 1 (opcode 19). The same in AMD CDNA 4, AMD CDNA 3, AMD CDNA 2, AMD CDNA 1, AMD RDNA 4, AMD RDNA 3.5, AMD RDNA 3.

Format SOPK
Width 32 bits
Opcode 18
Identifier 0xB9000000

Operands

  • SIMM16
    Written. Reference to a hardware register that is manipulated by getreg or setreg. This operand encodes the ID of the register to access and allows access to a subset of the full register by specifying an offset and size in bits. Data format: 16 bits of arbitrary data. (OPR_HWREG, FMT_NUM_B16)
  • SDST
    Read. All scalar destination operands. Data format: 32 bits of arbitrary data. (OPR_SDST, FMT_NUM_B32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOPK encoding (AMD CDNA 5).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Example

s_setreg_b32 0, s0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx13_asm_sopk.s). Not from an AMD document, and not authored here.

Sources