s_pack_hh_b32_b16 GPU Native ISA AMD Scalar

Scalar Arithmetic

s_pack_hh_b32_b16

Pack two 16-bit scalar values into a scalar register.

Encoding

Binary Layout (AMD CDNA 5)
10
31:30
0110100
29:23
SDST
22:16
SSRC1
15:8
SSRC0
7:0
 

The ENC_SOP2 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 52 in OP rebuilds 0x9A000000, an identifier AMD lists for this encoding. The same in the other 9 generations that define it.

Format SOP2
Width 32 bits
Opcode 52
Identifier 0x9A000000

Operands

  • SDST
    Written. All scalar destination operands. Data format: 32 bits of arbitrary data. (OPR_SDST, FMT_NUM_B32)
  • SSRC0
    Read. All scalar operands. Covers all operands that are allowed as scalar sources. Data format: 32 bits of arbitrary data. (OPR_SSRC, FMT_NUM_B32)
  • SSRC1
    Read. All scalar operands. Covers all operands that are allowed as scalar sources. Data format: 32 bits of arbitrary data. (OPR_SSRC, FMT_NUM_B32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOP2 encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

D0 = { S1[31 : 16].u16, S0[31 : 16].u16 }

Example

s_pack_hh_b32_b16 s0, 0, s2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources