s_setreg_imm32_b32 GPU Native ISA AMD Scalar

Scalar Arithmetic

s_setreg_imm32_b32

Write some or all of the LSBs of a 32-bit literal constant into a hardware register; this instruction requires a 32-bit literal constant.

Encoding

Binary Layout (AMD CDNA 5)
LITERAL
63:32
1011
31:28
10011
27:23
SDST
22:16
SIMM16
15:0
 

The SOPK_INST_LITERAL layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 19 in OP rebuilds 0x00000000B9800000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 20), AMD CDNA 3 (opcode 20), AMD CDNA 2 (opcode 20), AMD CDNA 1 (opcode 20), AMD RDNA 2 (opcode 21), AMD RDNA 1 (opcode 21). The same in AMD RDNA 4, AMD RDNA 3.5, AMD RDNA 3.

Format SOPK
Width 64 bits
Opcode 19
Identifier 0x00000000B9800000

Operands

  • SIMM16
    Written. Reference to a hardware register that is manipulated by getreg or setreg. This operand encodes the ID of the register to access and allows access to a subset of the full register by specifying an offset and size in bits. Data format: 16 bits of arbitrary data. (OPR_HWREG, FMT_NUM_B16)
  • LITERAL
    Read. 32-bit integer constant. Data format: 32 bits of arbitrary data. (OPR_SIMM32, FMT_NUM_B32)

In AMD's order, as its machine-readable ISA specification lists them for the SOPK_INST_LITERAL encoding (AMD CDNA 5).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Example

s_setreg_imm32_b32 0, 0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx13_asm_sopk.s). Not from an AMD document, and not authored here.

Sources