s_set_gpr_idx_idx GPU Native ISA AMD Scalar

Scalar Arithmetic

s_set_gpr_idx_idx

Set the index used in vector GPR indexing. S_SET_GPR_IDX_ON, S_SET_GPR_IDX_OFF, S_SET_GPR_IDX_MODE and S_SET_GPR_IDX_IDX are related instructions.

Encoding

Binary Layout (AMD CDNA 4)
101111101
31:23
SDST
22:16
00110010
15:8
SSRC0
7:0
 

The ENC_SOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 50 in OP rebuilds 0xBE803200, an identifier AMD lists for this encoding. The same in the other 3 generations that define it.

Format SOP1
Width 32 bits
Opcode 50
Identifier 0xBE803200

Operands

  • SSRC0
    Read. N/A Data format: N/A (OPR_SSRC, FMT_NUM_B32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOP1 encoding (AMD CDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

M0[7 : 0] = S0.u32[7 : 0].b8

Example

s_set_gpr_idx_idx 0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx8_asm_sop1.s). Not from an AMD document, and not authored here.

Sources