s_rfe_i64 GPU Native ISA AMD Scalar

Scalar Arithmetic

s_rfe_i64

AMDGPU SOP1 scalar instruction operating on i64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)

Also written as s_rfe_b64. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD CDNA 5)
101111101
31:23
SDST
22:16
01001010
15:8
SSRC0
7:0
 

The ENC_SOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 74 in OP rebuilds 0xBE804A00, an identifier AMD lists for this encoding. No other generation in the specification defines this instruction.

Format SOP1
Width 32 bits
Opcode 74
Identifier 0xBE804A00

Operands

  • SSRC0
    Read. Any scalar GPR operand including VCC and NULL. Data format: Signed 64-bit integral data. (OPR_SREG, FMT_NUM_I64)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOP1 encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Example

s_rfe_i64 vcc

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx13_asm_sop1.s). Not from an AMD document, and not authored here.

Sources