s_sleep_var GPU Native ISA AMD Scalar

Scalar Arithmetic

s_sleep_var

Cause a wave to sleep for up to ~8000 clocks, or to sleep until an external event wakes the wave up.

Encoding

Binary Layout (AMD CDNA 5)
101111101
31:23
SDST
22:16
01011000
15:8
SSRC0
7:0
 

The ENC_SOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 88 in OP rebuilds 0xBE805800, an identifier AMD lists for this encoding. The same in AMD RDNA 4.

Format SOP1
Width 32 bits
Opcode 88
Identifier 0xBE805800

Operands

  • SSRC0
    Read. All scalar operands. Covers all operands that are allowed as scalar sources. Data format: 32 bits of arbitrary data. (OPR_SSRC, FMT_NUM_B32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOP1 encoding (AMD CDNA 5).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Example

s_sleep_var 0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx13_asm_sop1.s). Not from an AMD document, and not authored here.

Sources