s_waitcnt_vmcnt GPU Native ISA AMD Scalar

Scalar Arithmetic

s_waitcnt_vmcnt

Wait for the VMCNT counter to be at or below the specified level.

Encoding

Binary Layout (AMD RDNA 3.5)
1011
31:28
11001
27:23
SDST
22:16
SIMM16
15:0
 

The ENC_SOPK layout from AMD's machine-readable ISA specification (AMD RDNA 3.5). Opcode 25 in OP rebuilds 0xBC800000, an identifier AMD lists for this encoding. Not the same in every generation: AMD RDNA 2 (opcode 24), AMD RDNA 1 (opcode 24). The same in AMD RDNA 3.

Format SOPK
Width 32 bits
Opcode 25
Identifier 0xBC800000

Operands

  • SDST
    Read. Special operand to indicate the result of the operation should be discarded. Data format: 32 bits of arbitrary data. (OPR_SDST_NULL, FMT_NUM_B32)
  • SIMM16
    Read. 16-bit integer constant. Data format: 16 bits of arbitrary data. (OPR_SIMM16, FMT_NUM_B16)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOPK encoding (AMD RDNA 3.5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Description

Wait for the VMCNT counter to be at or below the specified level. The VMCNT counter tracks the number of outstanding vector memory loads and atomics that do return data. When in 'all-in-order' mode, wait for all load and store vector memory events.

Example

s_waitcnt_vmcnt null, 0x1234

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources