s_wqm_b32 GPU Native ISA AMD Scalar

Scalar Arithmetic

s_wqm_b32

Given an active pixel mask in a scalar input, calculate whole quad mode mask for that input, store the result into a scalar register and set SCC iff…

Encoding

Binary Layout (AMD CDNA 5)
101111101
31:23
SDST
22:16
00011100
15:8
SSRC0
7:0
 

The ENC_SOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 28 in OP rebuilds 0xBE801C00, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 6), AMD CDNA 3 (opcode 6), AMD CDNA 2 (opcode 6), AMD CDNA 1 (opcode 6), AMD RDNA 2 (opcode 9), AMD RDNA 1 (opcode 9). The same in AMD RDNA 4, AMD RDNA 3.5, AMD RDNA 3.

Format SOP1
Width 32 bits
Opcode 28
Identifier 0xBE801C00

Operands

  • SDST
    Written. All scalar destination operands. Data format: Unsigned 32-bit integral data. (OPR_SDST, FMT_NUM_U32)
  • SSRC0
    Read. All scalar operands. Covers all operands that are allowed as scalar sources. Data format: Unsigned 32-bit integral data. (OPR_SSRC, FMT_NUM_U32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOP1 encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Description

Given an active pixel mask in a scalar input, calculate whole quad mode mask for that input, store the result into a scalar register and set SCC iff the result is nonzero. In whole quad mode, if any pixel in a quad is active then all pixels of the quad are marked active.

Semantics

tmp = 0U; declare i : 6'U; for i in 6'0U : 6'31U do tmp[i] = S0.u32[i & 6'60U +: 6'4U] != 0U endfor; D0.u32 = tmp; SCC = D0.u32 != 0U

Example

s_wqm_b32 s0, 0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources