s_wqm_b64 GPU Native ISA AMD Scalar

Scalar Arithmetic

s_wqm_b64

Given an active pixel mask in a scalar input, calculate whole quad mode mask for that input, store the result into a scalar register and set SCC iff…

Encoding

Binary Layout (AMD CDNA 5)
101111101
31:23
SDST
22:16
00011101
15:8
SSRC0
7:0
 

The ENC_SOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 29 in OP rebuilds 0xBE801D00, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 7), AMD CDNA 3 (opcode 7), AMD CDNA 2 (opcode 7), AMD CDNA 1 (opcode 7), AMD RDNA 2 (opcode 10), AMD RDNA 1 (opcode 10). The same in AMD RDNA 4, AMD RDNA 3.5, AMD RDNA 3.

Format SOP1
Width 32 bits
Opcode 29
Identifier 0xBE801D00

Operands

  • SDST
    Written. All scalar destination operands. Data format: Unsigned 64-bit integral data. (OPR_SDST, FMT_NUM_U64)
  • SSRC0
    Read. All scalar operands. Covers all operands that are allowed as scalar sources. Data format: Unsigned 64-bit integral data. (OPR_SSRC, FMT_NUM_U64)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOP1 encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related PTX Concepts

Execution Mask Manipulation ↗
equivalent with restrictions
activemask (PTX)

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Description

Given an active pixel mask in a scalar input, calculate whole quad mode mask for that input, store the result into a scalar register and set SCC iff the result is nonzero. In whole quad mode, if any pixel in a quad is active then all pixels of the quad are marked active.

Semantics

tmp = 0ULL; declare i : 6'U; for i in 6'0U : 6'63U do tmp[i] = S0.u64[i & 6'60U +: 6'4U] != 0ULL endfor; D0.u64 = tmp; SCC = D0.u64 != 0ULL

Example

s_wqm_b64 s[0:1], 0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources