s_rfe_b64 GPU Native ISA AMD Scalar
S RFE B64 Scalar Arithmetic
s_rfe_b64
Return from the exception handler.
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (SOP1)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
Related
More in Scalar Arithmetic
Reference
AMDGPU / GFX ISA
Description
Return from the exception handler. Clear the wave's PRIV bit and then jump to an address specified by the scalar input. The argument is a byte address of the instruction to jump to; this address is likely derived from the state passed into the trap handler. This instruction may only be used within a trap handler.
Semantics
WAVE_STATUS.PRIV = 1'0U;
PC = S0.i64
Example
s_rfe_b64 vccA real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 124. - LLVM MC assembler tests for AMDGPU (gfx11) ↗ - LLVM Project