szext GPU Virtual ISA NVIDIA

szext Integer Arithmetic Instructions

szext.mode.type d, a, b;

Sign-extends or zero-extends an N-bit value from operand a where N is specified in operand b.

Encoding

PTX is a virtual instruction set. It has no single, stable native binary encoding - the compiler lowers this instruction to different native machine code depending on the selected NVIDIA target architecture (compute capability). This page intentionally shows no bit-diagram; see the target/version requirements below for what governs how this instruction compiles.
PTX ISA Version Introduced PTX ISA 7.6
Minimum Target sm_70

Syntax Forms

One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.

Syntax Data Types State Space(s) Modifiers Min. Target Description
szext.mode.type d, a, b; sm_70 Sign-extends or zero-extends an N-bit value from operand a where N is specified in operand b. The resulting value is stored in the destination operand d. For the. (see the official PTX ISA docs for the full description)

Operands

  • d
    Destination register
  • a
    Source operand
  • b
    Source operand

At a Glance

Data Types -

Related AMDGPU Concepts

Sign/Zero Extend ↗
equivalent with restrictions
s_sext_i32_i16 (AMDGPU)
s_sext_i32_i8 (AMDGPU)

Related

More in Integer Arithmetic Instructions

Reference

NVIDIA PTX ISA

Description

Sign-extends or zero-extends an N-bit value from operand a where N is specified in operand b. The resulting value is stored in the destination operand d. For the.s32 instruction type, the value in a is treated as an N-bit signed value and the most significant bit of this N-bit value is replicated up to bit 31. For the.u32 instruction type, the value in a is treated as an N-bit unsigned number and is zero-extended to 32 bits. Operand b is an unsigned 32-bit value. If the value of N is 0, then the result of szext is 0. (see the official PTX ISA docs for the full description)

Semantics

b1 = b & 0x1f; too_large = (b >= 32 && .mode == .clamp) ? true : false; mask = too_large ? 0 : (~0) << b1; sign_pos = (b1 - 1) & 0x1f; if (b1 == 0 || too_large || .type != .s32) { sign_bit = false; } else { sign_bit = (a >> sign_pos) & 1; } d = (a & ~mask) | (sign_bit ? mask | 0);

Examples

szext.clamp.s32 rd, ra, rb;
szext.wrap.u32  rd, 0xffffffff, 0; // Result is 0.

Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.

Sources