mul24 GPU Virtual ISA NVIDIA

mul24 Integer Arithmetic Instructions

mul24.mode.type d, a, b;

Compute the product of two 24-bit integer values held in 32-bit source registers, and return either the high or low 32-bits of the 48-bit result.

Encoding

PTX is a virtual instruction set. It has no single, stable native binary encoding - the compiler lowers this instruction to different native machine code depending on the selected NVIDIA target architecture (compute capability). This page intentionally shows no bit-diagram; see the target/version requirements below for what governs how this instruction compiles.
PTX ISA Version Introduced PTX ISA 1.0
Minimum Target sm_10

Syntax Forms

One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.

Syntax Data Types State Space(s) Modifiers Min. Target Description
mul24.mode.type d, a, b; sm_10 Compute the product of two 24-bit integer values held in 32-bit source registers, and return either the high or low 32-bits of the 48-bit result.

Operands

  • d
    Destination register
  • a
    Source operand
  • b
    Source operand

At a Glance

Data Types -

Related AMDGPU Concepts

24-Bit Multiply ↗
equivalent with restrictions
v_mul_i32_i24 (AMDGPU)
v_mul_u32_u24 (AMDGPU)

Related

More in Integer Arithmetic Instructions

Reference

NVIDIA PTX ISA

Semantics

t = a * b; d = t<47..16>; // for .hi variant d = t<31..0>; // for .lo variant

Examples

mul24.lo.s32 d,a,b;   // low 32-bits of 24x24-bit signed multiply.

Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.

Sources