v_mul_i32_i24 GPU Native ISA AMD Vector

Vector Arithmetic

v_mul_i32_i24

Multiply two signed 24-bit integer inputs and store the result as a signed 32-bit integer into a vector register.

Encoding

Binary Layout (AMD CDNA 5)
0
31
001001
30:25
VDST
24:17
VSRC1
16:9
SRC0
8:0
 

The ENC_VOP2 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 9 in OP rebuilds 0x12000000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 6), AMD CDNA 3 (opcode 6), AMD CDNA 2 (opcode 6), AMD CDNA 1 (opcode 6). The same in AMD RDNA 4, AMD RDNA 3.5, AMD RDNA 3, AMD RDNA 2, AMD RDNA 1.

Format VOP2
Width 32 bits
Opcode 9
Identifier 0x12000000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Signed 32-bit integral data. (OPR_VGPR, FMT_NUM_I32)
  • SRC0
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: Signed 32-bit integral data. (OPR_SRC, FMT_NUM_I32)
  • VSRC1
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Signed 32-bit integral data. (OPR_VGPR, FMT_NUM_I32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP2 encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

This opcode is expected to be as efficient as basic single-precision opcodes since it utilizes the single-precision floating point multiplier. See also V_MUL_HI_I32_I24.

Related PTX Concepts

24-Bit Multiply ↗
equivalent with restrictions
mul24 (PTX)

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

D0.i32 = 32'I(S0.i24) * 32'I(S1.i24)

Example

v_mul_i32_i24 v5, -1, v2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources