v_or_b32 GPU Native ISA AMD Vector

V OR B32 Vector Arithmetic

v_or_b32

Calculate bitwise OR on two vector inputs and store the result into a vector register.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP2) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOP2
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Input and output modifiers not supported.

Related PTX Concepts

Bitwise OR ↗
equivalent with restrictions
or (PTX)

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

D0.u32 = (S0.u32 | S1.u32)

Example

v_or_b32 v5, -1, v2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.

Sources