v_rcp_f32 GPU Native ISA AMD Vector
Vector Arithmetic
Calculate the reciprocal of the single-precision float input using IEEE rules and store the result into a vector register.
Encoding
The ENC_VOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 42 in OP rebuilds 0x7E005400, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. Not the same in every generation: AMD CDNA 4 (opcode 34, field layout), AMD CDNA 3 (opcode 34, field layout), AMD CDNA 2 (opcode 34, field layout), AMD CDNA 1 (opcode 34, field layout), AMD RDNA 3.5 (field layout), AMD RDNA 3 (field layout), AMD RDNA 2 (field layout), AMD RDNA 1 (field layout). The same in AMD RDNA 4.
Operands
-
VDST
Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 32-bit single-precision floating point value. (OPR_VGPR, FMT_NUM_F32) -
SRC0
Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: 32-bit single-precision floating point value. (OPR_SRC, FMT_NUM_F32)
In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP1 encoding (AMD CDNA 5).
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
1ULP accuracy. Accuracy converges to < 0.5ULP when using the Newton-Raphson method and 2 FMA operations. Denormals are flushed.
Related PTX Concepts
Related
More in Vector Arithmetic
Reference
Semantics
Example
V_RCP_F32(0xff800000) => 0x80000000 // rcp(-INF) = -0
V_RCP_F32(0xc0000000) => 0xbf000000 // rcp(-2.0) = -0.5
V_RCP_F32(0x80000000) => 0xff800000 // rcp(-0.0) = -INF
V_RCP_F32(0x00000000) => 0x7f800000 // rcp(+0.0) = +INFReproduced from AMD's official "AMD Instinct MI300" ISA Reference Guide for technical accuracy.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 196. - AMD Machine-Readable GPU ISA Specification ↗ - Advanced Micro Devices, Inc.